Architectural features

AMD’s x86-64 instruction set (later renamed AMD64) is an extension of Intel’s IA-32 (x86-32) architecture, created as an alternative to Intel and Hewlett Packard’s radically different IA-64 architecture which has received a relatively cool market reception in many market sectors, and which was protected from cloning by a number of patents. The primary defining characteristic of AMD64 is its support for 64-bit general purpose registers, 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses. The designers took the opportunity to make other improvements as well. The most significant changes include:
Full support for 64-bit integers: All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., are now directly supported for 64-bit integers. Pushes and pops on the stack are always in eight-byte strides, and pointers are eight bytes wide.
Additional registers: In addition to increasing the size of the general-purpose registers, their number is increased from eight (i.e. eax,ebx,ecx,edx,ebp,esp,esi,edi) in x86-32 to 16. It is therefore possible to keep more local variables in registers rather than on the stack and to let registers hold frequently accessed constants — this should be a significant area of speed improvement for software with computationally-intensive deeply-nested loops; arguments for small and fast subroutines may also be passed in registers to a greater extent. However, more registers also involves more saving and restoring of register contents, and AMD64 still has fewer registers than many common RISC processors (which typically have 31-64 registers) or VLIW-like machines such as the IA-64 (which has 128 registers).
Additional XMM registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.
Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (248 bytes). This limit can be raised in future implementations to 16 exbibytes (264 bytes). This is compared to just 4 gibibytes for 32-bit x86. This means that very large files can be operated on by mapping the entire file into the process’s address space (which is generally faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.
Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (240 bytes); the architecture permits extending this to 4 pebibytes (252 bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.
Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.
SSE instructions: The original AMD64 architecture adopted Intel’s SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set’s IEEE 80-bit precision, with the choice of either IEEE 32-bit or 64-bit floating-point math. This provides floating-point operations compatible with many other modern CPUs. The SSE and SSE2 instructions have also been extended to support the eight new XMM registers. SSE and SSE2 are available in 32-bit mode in modern x86 processors; however, if they’re used in 32-bit programs, those programs will only work on systems with processors that support them. This is not an issue in 64-bit programs, as all processors that support AMD64 support SSE and SSE2, so using SSE and SSE2 instructions instead of x87 instructions doesn’t reduce the set of machines on which the programs will run. Since SSE and SSE2 are generally faster than, and duplicate most of the features of, the traditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.
No-Execute bit: The “NX” bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged “no execute” will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via “buffer overrun” or “unchecked buffer” attacks. A similar feature has been available on x86 processors since the 80286 as an attribute of segment descriptors; however, this works only on an entire segment at a time. Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of 0 and a size of 4 GiB. AMD was the first x86-family vendor to support no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.
Removal of older features: A number of “system programming” features of the x86 architecture are not used in modern operating systems and are not available on AMD64 in long (64-bit and compatibility) mode. These include segmented addressing (although the FS and GS segments remain in vestigial form, for compatibility with Windows code), the task state switch mechanism, and Virtual-8086 mode. These features do of course remain fully implemented in “legacy mode,” thus permitting these processors to run 32-bit and 16-bit operating systems without modification. If, at some point in the future, 32-bit and 16-bit code using those features is no longer used, support for them might be removed from hardware to streamline processor design and save manufacturing costs. These features could be emulated in the operating system to preserve legacy application compatibility, as with DOSBox and similar emulators.

Virtual Address Space Details

Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and any chips known to be in the planning stages) do not allow the entire virtual address space of 264 bytes (16 exbibytes, or about 18×1018 bytes) to be used. Most operating systems and applications will not need such a large address space for the forseeable future (for example, Windows implementations for AMD64 are only populating 16 tebibytes, or 44 bits’ worth), so supporting such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD therefore decided that, in the first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation (page table lookup). However, bits 48 through 63 of any virtual address must be copies of bit 47 (in a manner akin to sign extension), or an exception will be raised. Addresses complying with this rule are referred to as “canonical form.” Canonical form addresses run from 0 through 7FFF`FFFFFFFF, and from FFFF8000`00000000 through FFFFFFFF`FFFFFFFF, for a total of 248 bytes or 256 tebibytes of usable virtual address space.

This “quirk” allows an important feature for later scalability to true 64 bit addressing: traditionally, operating systems take one half of the address space for themselves (usually the higher half, named kernel space) and leave the other to applications (user space). The “canonical address” design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000`00000000 and “grows upwards” as more virtual address bits become available, while the higher half is “docked” to the top of the address space and grows downwards.

Current 48 bit implementation

56 bit implementation

Full 64 bit implementation

Operating mode explanation

There are two primary modes of operation for this architecture:
Long Mode
The intended primary mode of operation of the architecture; it is a combination of the processor’s native 64-bit mode and a 32-bit/16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit, 32-bit and 16-bit (or 80286) protected mode applications may be supported.
Since the basic instruction set is the same, there is no major performance penalty for executing x86 code. This is unlike Intel’s IA-64, where differences in the underlying ISA means that running 32-bit code is like using an entirely different processor. However, on AMD64, 32 bit x86 applications may still benefit from a 64-bit recompile, due to the additional registers in 64-bit code, which a high-level compiler can use for optimization.
Legacy Mode
The mode used by 16-bit (protected mode or real mode) and 32-bit operating systems. In this mode, the processor acts just like an x86 processor, and only 16-bit or 32-bit code can be executed. 64-bit programs will not run.

Market analysis

AMD64 represents a break with AMD’s past behavior of following Intel’s standards, but repeats Intel’s earlier behavior of extending the x86 architecture, from the 16-bit 8086 to the 32-bit 80386 and beyond, without ever removing backwards compatibility.

It was believed at one point that 64-bit RISC chips such as the DEC Alpha would eventually replace the outdated and quirky x86 architecture. Part of the reason this did not happen was the vast investment in application software for x86 systems. AMD64 effectively migrates the x86 architecture into a fully 64-bit environment, while maintaining legacy compatibility with x86 applications.

As of 2006, there has still been a lack of adoption of 64-bit software for most consumer and business applications. Most current software applications don’t need to address more than 2 GB of memory. Nevertheless, the cost-effectiveness of the chips has been that AMD has been able to capture a much larger share of desktop and laptop sales at the expense of Intel simply because of the performance for cost and growth capability should 64 bit applications become common. Intel in the summer of 2006 had announced a substantial reduction in net revenue and major restructuring.

Implementations

The following processors implement the AMD64 architecture:

- An AMD Athlon 64 processor
- AMD K8
- AMD Athlon 64
- AMD Athlon 64 X2
- AMD Athlon 64 FX
- AMD Opteron
- AMD Turion 64
- AMD Sempron (’Palermo’ E6 stepping and all ‘Manila’ models)