After long time waitin for the DDR3 Ram, at least here any small review of DDR3. The Memory are Samsung 2 modules DDR3 533 MHz with SPD CL 7-7-7-20.
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On modern systems, memory is very rarely, if ever, overclocked for the sake of overclocking memory. Lemme rephrase that, people don’t overclock memory to make it run higher than what is actually needed. There are many instances where memory is even underclocked. You first determine the default frequency of your memory, 1MHz higher than that frequency is the point where overclocking begins. Now how do you increase that frequency? As previously discussed, best performance on all platforms is gained by running the memory frequency synchronously with speed of the FSB. This means that for every 1MHz the FSB is increased, so too will the frequency of memory clock. So in effect, memory overclocking is just a part of overclocking your processor. They are done simultaneously. Since FSB frequency and Memory frequency are most times made to be the same, this poses a problem - as overclockers look for the highest possible FSB while the memory may struggle behind because it’s not able to keep. Other aspects to memory overclocking are memory timings and of course the amount of voltage supplied. Unlike CPU overclocking or video card tweaking, adjusting memory timings and frequencies offers very little physical risk to your system, other than the possibility of a windows failure to load or a program failure while testing. The memory will either be able to handle the overclocking/tweaking, handle it with instability or not handle it all. There are no grey areas in between, it either does, does with lots of problems, or doesn’t at all. This makes it a bit simpler to quickly find the precise limits of any memory. The memory timings can also play a role in how far the memory will go, in keeping with the FSB. Lower timings (numbers) will hinder how fast the memory can run, while higher timings allow for more memory speed. So which is better, lower timings or higher memory speeds? Why not both? Overall data throughput depends on bandwidth and latencies. Peak bandwidth is important for certain applications that employ mostly streaming memory transfers. In these applications, the memory will burst the data, many words after each other. Only the very first word will have a latency of maybe several cycles, but all other words will be delivered one after another. Other applications with more random accesses, like games, will get more mileage out of lower latency timings. So weigh the importance of higher memory clocks against lower latency timings, and decide which is most important for your application.

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Memory performance is not entirely determined by bandwidth, but also the speeds at which it responds to a command or the times it must wait before it can start or finish the processes of reading or writing data. These are memory latencies or reaction times (timings). Memory timings control the way your memory is accessed and can be either a contributing factor to better or worse ‘real-world’ performance of your system.

Internally DRAM has a huge array of cells that contain data. (If you’ve ever used Microsoft’s Excel, try and picture it that way) A pair of row and column addresses can uniquely address each cell in the DRAM. DRAM communicates with a memory controller through two main groups of signals: Control-Address signals and Data signals. These signals are sent to the RAM in order for it to read/write data, address and control. The address is of course where the data is located on the memory banks, and the control signals are various commands needed to read or write. There are delays before a control signal can be executed or finish and this is where we get memory timings. The standard format for memory timings are most often expressed as a string of four numbers, separated by dashes, from left to right or vice-versa like this 2-2-2-5 [CAS-tRP-tRCD-tRAS] . These values represent how many clock cycles long each delay is but are not expressed in the order in which they occur. Different bioses will display them differently and there maybe additional options (timings) available.

Definition of Timing

In most motherboards, numerous settings can be found to optimize your memory. These settings are often found the Advanced Chipset section of the popular award bioses. In certain instances, the settings maybe placed in odd locations, so please consult your motherboard manual for specific information. Below are common latency options:

• Command rate - is the delay (in clock cycles) between when chip select is asserted (i.e. the RAM is selected) and commands (i.e. Activate Row) can be issued to the RAM. Typical values are 1T (one clock cycle) and 2T (two clock cycles).
• CAS (Column Address Strobe or Column Address Select) - is the number of clock cycles (or Ticks, denoted with T) between the issuance of the READ command and when the data arrives at the data bus. Memory can be visualized as a table of cell locations and the CAS delay is invoked every time the column changes, which is more often than row changing.
• tRP (RAS Precharge Delay) - is the speed or length of time that it takes DRAM to terminate one row access and start another. In simpler terms, it means switching memory banks.

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DDR Dual Channel

Most of today’s mainstream chipsets are using some form of dual channel to supply processors with bandwidth. The nForce and nForce2 are, at this time, the only two chipsets to supply dual-channel goodness for the Athlon XP. The original nForce was not on the same performance and stability level as the competitor VIA’s chipset was, but the new and improved dual-channel DDR400 nForce2 has been a smash success — in fact, is today’s de facto choice for performance-minded / overclocker AMD desktop buyers. VIA is now about to release a Dual Channel chipset for the Athlon XP/Duron family called the KT880.

Take note that the memory isn’t dual channel, the platform is. In fact there is no such thing as dual channel memory. Rather, it is most often a memory interface composed of two (or more) normal memory modules coordinated by the chipset on the motherboard, or in the case of the AMD64 processors, coordinated by the integrated memory controller. But for the sake of simplicity, we refer to DDR dual channel architecture as dual channel memory.

The nforce2 platform has two 64 bit memory controllers (which are independent of each other) instead of just a single controller like other chipsets. These two controllers are able to access “two channels” of memory simultaneously. The two channels, together, handle memory operations more efficiently than one module by utilizing the bandwidth of two modules (or more) combined. By combining DDR400 (PC3200) with dual memory controllers, the nForce2 could offer up to 6.4 GB/sec of bandwidth in theory.

However, this extra bandwidth produced by dual channel cannot be fully utilitized by the Athlon XP and Duron family (K7) of processors. Data(bandwidth) will reach these processors no sooner than the system bus (FSB) allows them, and the processor therefore cannot derive an advantage from memory operating faster than DDR266 when operating on a 133/266Mhz FSB, DDR333 with a 166/333Mhz FSB or DDR400 at 200/400Mhz FSB even in single channel mode. Visualize a four lane highway, symbolizing your Dual Channel configuration. As you go along the highway you come up to a bridge that is only 2 lanes wide. That bridge is the restriction posed by the dual-pumped AMD FSB. Only two lanes of traffic may pass through the bridge at any one time. That’s the way it is, with the K7 processors and Dual Channel chipsets.

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The speed of DDR is usually expressed in terms of its “effective data rate”, which is twice its actual clock speed. PC3200 memory, or DDR400, or 400 MHz DDR, is not running at 400 MHz, it is running at 200 MHz. The fact that it accomplishes two data transfers per clock cycle gives it nearly the same bandwidth as SDRAM running at 400 MHz, but DDR400 is indeed still running at 200 MHz.

Actual clock speed/effective transfer rate
DDR:
100/200 MHz => DDR200 or PC1600
133/266 MHz => DDR266 or PC2100
166/333 MHz => DDR333 or PC2700
185/370 MHz => DDR370 or PC3000
200/400 MHz => DDR400 or PC3200
217/433 MHz => DDR433 or PC3500
233/466 MHz => DDR466 or PC3700
250/500 MHz => DDR500 or PC4000
267/533 MHz => DDR533 or PC4200
283/566 MHz => DDR566 or PC4500

DDR2:

266/533MHz=>DDR2 533 or PC 4300
333/667MHz=>DDR2 667 or PC 5400
400/800Mhz=>DDR2 800 or PC 6400
500/1000MHz=> DDR2 1000 or PC8000
etc

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