In International Solid State Circuits Conference (ISSC), IBM will explain new details of technology memory. Embedded DRAM (eDRAM). This memory was designed to be used in CPU as cache. Despite as category dynamic RAM, but had the characteristics that almost equally fast from memory SRAM, but with the measurement die that was far more smaller.  Maximal around half of the measurement core CPU, that for the certain situation then.

The fact is, this memory was not suitable if must be used in an integrated into CPU, because of eDRAM had l a big atency. The difference with the memory SRAM, that SRAM had small latency.But SRAM was to have to be needed bigger dier. As the information, for one cell memory (1 bit the data), DRAM only needed a1 transistor and the capacitor but SRAM needed 4 as far as 6 transistors.

According to IBM, for the kind of eDRAM memory at this time has been made the prototype that went with latency that only 1.5ns and 2ns for one cycle time. Also used technology 65nm. This matter indeed made the speed eDRAM quite competitive with the speed memory SRAM that at this time often was used.
For his implementation, IBM just will begin used the kind memory this for the generation of the technology processor 45nm, around 2008.