Memory Basic
DRAM Memory Technologies
DRAM is available in several different technology types. At their core, each technology is quite similar to the one that it replaces or the one used on a parallel platform. The differences between the various acronyms of DRAM technologies are primarily a result of how the DRAM inside the module is connected, configured and/or addressed, in addition to any special enhancements added to the technology.
There are five well-known technologies:
Synchronous DRAM (SDRAM)
An older type of memory that quickly replaced earlier types and was able to synchronize with the speed of the system clock. SDRAM started out running at 66 MHz, faster than previous technologies and was able to scale to 133 MHz (PC133) officially and unofficially up to 180 MHz. As processors grew in speed and bandwidth capability, new generations of memory such as DDR and RDRAM were required to get proper performance.
Double Data Rate Synchronous DRAM (DDR SDRAM)
DDR SDRAM is a lot like regular SDRAM (Single Data Rate) but its main difference is its ability to effectively double the clock frequency without increasing the actual frequency, making it substantially faster than regular SDRAM. This is achieved by transferring data not only at the rising edge of the clock cycle but also at the falling edge. A clock cycle can be represented as a square wave, with the rising edge defined as the transition from ‘0’ to ‘1’, and the falling edge as ‘1’ to ‘0’. In SDRAM, only the rising edge of the wave is used, but DDR SDRAM references both, effectively doubling the rate of data transmission. For example, with DDR SDRAM, a 100 or 133 MHz memory bus clock rate yields an effective data rate of 200 MHz or 266 MHz, respectively. DDR modules utilize a 184-pin DIMM (Dual Inline Memory Module) packaging which, like SDRAM, allows for a 64 bit data path, allowing faster memory access with single modules over previous technologies. Although SDRAM and DDR share the same basic design, DDR is not backward compatible with older SDRAM motherboards and vice-versa.
It is important to understand that while DDR doubles the available bandwidth, it generally does not improve the latency of the memory as compared to an otherwise equivalent SDRAM design. In fact the latency is slightly degraded, as there is no free lunch in the world of electronics or mechanics. So while the performance advantage offered by DDR is substantial, it does not double memory performance, and for some latency-dependant tasks does not improve application performance at all. Most applications will benefit significantly, though
Developed by Rambus, Inc., RDRAM, or Rambus DRAM was a totally new DRAM technology that was aimed at processors that needed high bandwidth. RAMBUS, Inc. agreed to a development and license contract with Intel and that lead to Intel’s PC chipsets supporting RDRAM. RDRAM comes in PC600, PC700, PC800 and PC1066 speeds. Specific information on this memory technology can be found at the www.rambus.com
Unfortunately for Rambus, dual channel DDR memory solutions have proved to be quite efficient at delivering about the same levels of performance as RDRAM at a much lower cost. Intel eventually dropped RDRAM support in their new products and chose to follow the DDR dance, at which point RDRAM almost completely fell off the map. Rambus, SiS, Asus and Samsung have now teamed up and are planning a new RDRAM solution (the SiS 659 chipset) providing 9.6 GB/s of bandwidth for the Pentium 4. It will be an uphill battle to get RDRAM back in the mainstream market without Intel’s support.
DDR2 SDRAM
Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called double pumping). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, allowing transfers from two different cells to occur in the same memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
DDR2’s bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits wide, whereas it is 2 bits wide for DDR and 8 bits wide for DDR3.
One cost of these optimizations is increased latency, as the cells take twice as long (in terms of bus cycles) to produce a result, and additional buffering adds yet more delay. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 3 and 9 cycles. Because of this higher latency, DDR SDRAM running at the same bus speed as DDR2 is generally considered superior; DDR2 is, however, able to run at substantially higher bus speeds.
Another cost of the increased speed is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR and SDRAM. This packaging change was necessary to maintain signal integrity at higher speeds.
Although the effective clock speeds of DDR2 are higher than for DDR, the total performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.
The increased packaging cost and lack of initial relative benefit over DDR has delayed the rate of adoption of DDR2 over the previous memory technology compared to DDR and SDRAM. Other factors delaying the DDR2 adoption rate have been that the main semiconductor vendors have recently shifted more focus to the relatively more profitable NAND flash market.
Power savings are achieved primarily due to an improved manufacturing process, resulting in a drop in operating voltage (1.8 V compared to DDR’s 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available speed.
Soon….. DDR3
The memory comes with a promise of a power consumption reduction of 40% compared to current commercial DDR2 modules, due to DDR3’s 90 nm fabrication technology, allowing for lower operating currents and voltages (1.5 V, compared to DDR2’s 1.8 V or DDR’s 2.5 V). “Dual-gate” transistors will be used to reduce leakage of current.
DDR3’s prefetch buffer width is 8 bit, whereas DDR2’s is 4 bit, and DDR’s is 2 bit.
Theoretically, these modules could transfer data at the effective clockrate of 400-800 MHz (for a single clock bandwidth of 800-1600 MHz), compared to DDR2’s current range of 200-533 MHz (400-1066 MHz) or DDR’s range of 100-300 MHz (200-600 MHz). To date, such bandwidth requirements have been mainly on the graphics market, where fast transfer of information between framebuffers is required.
DDR3 sticks maintain the 240-pin DIMM interface of DDR2, allowing DDR3 compatible chipsets to host DDR2 modules (though not both types at once).
Prototypes were announced in early 2005, while the DDR3 specification is expected to be publicly available in mid-2007. Supposedly, Intel has preliminarily announced that they expect to be able to offer support for it in mid - end of 2007 with a version of their upcoming Bearlake chipset. AMD & Intel indicates their own adoption of DDR3 to come in 2008.
The GDDR3 memory, with a similar name but an entirely dissimilar technology, has been in use for several years in high-end graphic cards such as ones from NVIDIA or ATI Technologies, and as main system memory on the Microsoft Xbox 360.
Source from the forum and wikipedia*
