The NetBurst Microarchitecture is the name given to the architecture that succeeded the P6 microarchitecture in the x86 family of CPUs made by Intel. The first one to use this architecture was the Willamette core, released in late 2000. It was the first in line of the Pentium 4 CPUs, and ever since then, Pentium 4 CPUs have only used NetBurst. In mid 2001, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4 based Celeron CPUs also use the NetBurst architecture. Certain groups refer to NetBurst as Intel P7 or Intel 80786 when comparing to previous chips, although these are not official names.

Technology

The NetBurst architecture basically includes features such as “Hyper Pipelined Technology” and “Rapid Execution Engine” which are firsts in this particular microarchitecture.

Hyper Pipelined Technology

Intel chose this name for the 20 stage pipeline within the Willamette architecture. This is a significant increase in the number of stages when compared to the PIII which had only 10 stages in its pipeline. The Prescott achitecture, the last core of the Pentium 4, has an amazing 31 stage pipeline. Although this is an impressive number, a longer pipeline always has its inherent disadvantages, mainly a reduced number of instructions per cycle. This, however, is annulled by the fact that the higher number of stages in the pipeline allow the CPU to have higher clock speeds which will technically offset any loss in performance due to the reduced IPC. Another drawback of having too many stages in a pipeline is the number of stages that need to be traced back in case the branch predictor makes a mistake. The longer the pipeline, the further back in the process you have to trace in order to rectify the mistake, which increases the penalty paid for a misprediction. Keeping this in mind, Intel came up with the second feature in the NetBurst architecture, which is known as the “Rapid Execution Engine.” In addition to this, Intel has invested a great deal into its branch prediction technology, which is capable at least 80% correct branch predictions.

Rapid Execution Engine

As per this technology, the ALUs in the core of the CPU actually operate at twice the core clock frequency. This means that in a 3.5 GHz CPU the ALUs will effectively be operating at an impressive 7 GHz. The reason behind this is to generally make up for the low IPC count; additionally this considerably enhances the integer performance of the CPU. The downside is that certain instructions are now much slower (relatively and absolutely) than before, making optimization for multiple target CPUs difficult. An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the 386 (and is also present on Athlon and Hammer).

Execution Trace Cache

Within the L2 cache of the CPU, Intel has incorporated what it calls an Execution Trace Cache. This cache stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU can directly access the decoded micro-ops from the trace cache, thereby saving a considerable amount of time. Moreover the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution.

Despite all these enhancements, today the NetBurst architecture has not proved to be very successful in terms of performance. With this architecture, Intel was looking to touch speeds of 10 GHz, but with rising clock speed, Intel has faced increasing problems with keeping power dissipation within acceptable limits. Intel has reached the limits at a speed of 3.8 GHz and has encountered problems trying to hit even that. As a result, newer Intel roadmaps clearly indicate abandoning NetBurst and adopting a newer microarchitecture, known as Core Microarchitecture (inspired by the Pentium M), to help them achieve their goals.

Revisions

Intel replaced the original Willamette core with a redesigned version of the NetBurst architecture called Northwood in January of 2002. The Northwood design combined an increased cache size, a smaller 130 nm fabrication process, and hyper-threading technology (although initially all models but the 3.06 GHz one had this feature disabled) to produce a more modern, higher-performing version of the NetBurst architecture.

In February of 2004, Intel introduced another, more radical revision of the architecture called Prescott. The Prescott was produced on a 90 nm process, and included several major design changes, including the addition of an even larger cache (from 512KB in the Northwood to 1MB, and later 2MB), a much larger instruction pipeline (31 stages as compared to 20 in the Northwood), a heavily improved branch predictor, the introduction of the SSE3 SIMD instructions, and later, the implementation of EM64T, Intel’s branding for their compatible implementation of the AMD64 64-bit version of the x86 architecture (as with hyper-threading, all Prescott chips have hardware to support this feature, but it was initially only enabled on high-end Xeon processors before being officially introduced in processors with the Pentium brand). Despite having many new features, the Prescott often performed worse than a similarly-clocked Northwood, and many engineers felt that the real-world performance of the processor was compromised by attempting to achieve the highest clock speed possible. Power consumption and heat dissipation also became a major issue with Prescott, as it is one of the hottest-running and power-hungry microprocessors in history. Power and heat concerns have thus far prevented Intel from releasing a Prescott clocked above 3.8 GHz, or a mobile version of the core. This has led some computer enthusiasts to coin the term “the Intel Face-Plant”, mocking the apparent failure of Prescott.

Intel has also released a dual-core version of the NetBurst architecture called Smithfield, which is actually two Prescott cores in a single die, and later Presler, which consists of two Cedar Mill cores on two separate dies (Cedar Mill being the 65nm die-shrink of Prescott).

Future

Intel has replaced NetBurst with the Intel Core Microarchitecture, released in July 2006, which is more directly derived from 1995’s Pentium Pro than it is from NetBurst.

Presler, a core of Pentium D released in early 2006, is widely touted by analysts to be the last in the line of NetBurst, though the actual final Netburst chip will be the Tulsa core Xeon MP. The “Conroe” version of the Intel Core 2 processor, using the Intel Core Microarchitecture, is the successor to Presler.

NetBurst based chips

- Celeron
- Celeron D
- Pentium 4, since 2000
- Pentium D, since 2005
- Pentium Extreme Edition
- Xeon, since 2001